1. Field of the Invention
The present invention relates to a high-frequency switching device which switches two transmission routes of an RF signal.
2. Description of the Related Art
A high-frequency switching device is used in a cellular phone, a PHS (Personal Handy Phone System) or the like. Conventionally, a high-frequency switch having a circuit configuration utilizing on/off operations of a PIN diode is mainly incorporated in these systems. However, a switch having the configuration does not satisfy the downsizing requirement of devices in recent years. Therefore, switches using FETs have become mainstream. Further, a type of switch incorporating a control circuit has been noted recently. Since a switch of this type has only one control terminal, the system design burdens are reduced.
FIG. 1A shows an example of the circuit configuration of an SPDT (Single Port Double Throw) switch incorporating an inverter circuit.
As shown in FIG. 1A, the SPDT switch operates using a positive voltage as a single power source. Since the SPDT switch has two transmission routes, it requires two control signals inverted relative to each other. Therefore, the SPDT switch having a single input terminal for control signals is attained by incorporating an inverter circuit in the switch. The SPDT switch has a switch section 210 and a control section (inverter section) 230. A GaAs FET is generally used as an FET contained in the SPDT switch in a microwave band. It is desirable that the SPDT switch be implemented as an MMIC (Monolithic Microwave IC), comprising a single GaAs chip and semiconductor elements formed thereon. In the MMIC, since a plurality of terminals can be integrated to one terminal, external members can be reduced. In addition, the SPDT switch can be implemented in a compact package having a small number of pins. FIG. 1A shows a circuit configuration based on the assumption that the switch is implemented in a six-pin package.
An RF terminal 201 is connected to an RF terminal 202 via a current path of an FET 211. The RF terminal 202 is connected to a power source terminal 204 via a current path of an FET 213. The RF terminal 201 is also connected to an RF terminal 203 via a current path of an FET 212. The RF terminal 203 is connected to the power source terminal 204 via a current path of an FET 214. In the following descriptions, the FETs 211 and 212 are called the through FETs, while the FETs 213 and 214 are called the shunt FETs. The power source terminal 204 is grounded via a capacitor element 220, and receives power supplied through a resistor element.
A control terminal 205 is connected to an input terminal 231 of the inverter section 230. It is connected to the gate of the shunt FET 214 via a resistor element 224 and to the gate of the through FET 211 via a resistor element 221. An output terminal 232 of the inverter section 230 is connected to the gate of the shunt FET 213 via a resistor element 223 and to the gate of the through FET 212 via a resistor element 222. The resistor elements 221 to 224 and a bias resistor element 225 for the through FETs 211 and 212 have high resistance of a value, for example, several kΩ.
In the SPDT switch operating by means of the power source voltage of 3V as a single power source, for example, when a control signal voltage of 0V is applied, the FET 211 is off and the FET 212 is on. Therefore, an RF signal transmits between the RF terminals 201 and 203. To the contrary, when a control signal voltage of 3V is applied, the FET 211 is on and the FET 212 is off. Therefore, an RF signal transmits between the RF terminals 201 and 202. Thus, the switch incorporating the inverter circuit can be controlled through one terminal.
The inverter section 230 has an E/D type inverter circuit 250 including a driver FET 252 and a load FET 251, and a source follower circuit 240 positioned in a stage before the inverter circuit 250. The source follower circuit 240 aims at a level shift of the voltage input to the gate of the driver FET 252, such that the maximum voltage does not exceed the Schottky voltage. Therefore, although the shift amount of the voltage is determined by two FETs 242 and 243, the number of FETs required for this purpose depends on the power source voltage. Of the aforementioned circuits, the FETs 211–214, 241–244 and 251 are depletion type FETs, and the FET 252 is an enhancement type FET.
The source follower 240 is necessary to keep the low-level potential output from the inverter circuit sufficiently low, thereby suppressing distortion when a large signal is input. In this description, the terms “high level” and “low level” respectively mean the level of the voltage output from the inverter circuit 250 when the signal “0” is input and the level of the voltage output from the inverter circuit 250 when the signal “1” is input.
If there is no source follower circuit 240, a Schottky current flows when the input voltage exceeds the Schottky voltage (approximately 0.7V). Then the potential of the low level is increase by a voltage drop in a source resistor of the FET 252. For example, when the input voltage is 3V, the voltage at the output terminal 232 is 0.8V. If the potential of the low level increases, a linear output cannot be obtained when a large signal is input, resulting in occurrence of distortion. To describe this phenomenon, it is assumed that a signal is input through the RF terminal 201 of the switch section 210 and output through the RF terminal 202 via the on-state through FET 211.
FIG. 1B shows the relationship between a gate-source voltage (Vgs) and a current in the off-state through FET 212. If the power source voltage is 3V and voltages of 3V and 0V are respectively applied to the gate terminals of the FET 211 and the FET 212, the gate-source voltage Vgs of the FET 212 is −3V. When an RF signal is input through the terminal 201, the voltage Vgs has an amplitude in accordance with the input voltage. When a large signal is input, the voltage Vgs exceeds the threshold voltage (Vth) in the FET 212. Therefore, the through FET 212, which has been in the off state, is turned on during a certain time period. When the through FET 212 is on, the current begins to flow to the terminal 203 and the waveform of the RF signal is deformed. Then, radio noise other than the fundamental, such as a second or third harmonic spurious, is generated. As a result, trouble may occur in the system. An increase in low-level potential shifts the voltage Vgs of the off-state through FET 212 to the positive side by the increased voltage. Consequently, the through FET 212 is turned on at a lower input voltage. As described above, the high-level and low-level potentials of the inverter circuit 150 greatly influences the distortion when a large signal is input. Therefore, these potentials must be fully taken into consideration when the inverter circuit is designed.
The high-frequency switching circuit having the source follower circuit 240 is described in, for example, U.S. patent application Ser. No. 09/264,003.
As mentioned above, the control switch incorporating an inverter circuit that has a single input terminal for control signals is mainly used for mobile devices, such as cellular phones. Since the mobile devices are battery-driven, they require reduction in power consumption. Therefore, it is desirable that the current consumed by the inverter circuit be as small as possible, specifically, 1 mA or less.
Reduction in gate width of FETs can satisfy the above requirement. As the gate width is reduced, the FETs are less resistant to surge. An FET having a relatively wide gate width of about, for example, 1 mm, can be used to constitute a switch circuit in order to reduce ON resistance. Therefore, surge is not a serious problem in an SPDT switch comprising only a switch circuit. However, an inverter circuit uses an FET having a gate width of 10 μm or smaller. Therefore, an SPDT switch incorporating an inverter circuit suffers from the problem of damage of the inverter circuit by surge, so that the SPDT switch cannot be operated.
In the case where a switch is implemented by an MMIC including a switch section and an inverter section formed on a single chip, a signal may be leaked from the switch section to the inverter section when a large signal is input. Then, the operation of the inverter circuit, driven by a small current, is liable to be unstable. For example, if a wire for transmitting an RF signal crosses over a wire connected to the output terminal of the inverter circuit, the RF signal will leak to the latter wire. In this case, fluctuations of the potential of the output terminal of the inverter circuit will be a problem. To describe this problem, with reference to FIG. 1A, a case is considered in which the power source voltage is 3V and the voltage at the control terminal 205 is 0V, so that the output terminal 232 of the inverter circuit 250 is 3V, and consequently a signal transmits from the RF terminal 201 to the RF terminal 203.
FIG. 1C shows influences of an input signal to the switch section on the potential of the output terminal of the inverter circuit. More specifically, it shows a change with time in potential of the output terminal 232 of the inverter circuit, where a crossover capacitance between the RF terminal 201 and the output terminal 232 is 100 fF and signals of 0 dBm and 20 dBm are input to the RF terminal 201. For input power of 0 bBm, the potential at the output terminal 232 does not substantially change. For input power of 20 dBm, on the other hand, the potential at the output terminal 232 ranges between 1V and 4V. For example, since the power source voltage is 3V, if the potential at the output terminal 232 is 1V, the gate-source voltage Vgs of the through FET 212 is −2V. Thus, if the threshold voltage Vth of the FET is −1.5V, the gate-source voltage Vgs of the FET 212 is smaller than the threshold voltage Vth. Therefore, the FET 212 cannot be turned on in this case, and the signal cannot pass through the FET 212 during this period of time. This matter is manifested as a distortion of a signal transmitting from the RF terminal 201 to the RF terminal 203, resulting in deterioration of input/output power characteristics. The leakage of the RF signal described above greatly influences distortion characteristics. The more the leakage of the RF signal resulting from the crossover capacitance, the less input power causes distortion. The leaked signal influences not only the output terminal, that is, a signal leaked from the switch section may influence the input terminal, the power source terminal and the GND terminal of the inverter circuit. However, since these terminals extend out of the package, measures against the influence can be taken: for example, a decoupling capacitance can be provided in the substrate. In contrast, the output terminal is formed inside the chip. It is difficult to provide an effective decoupling capacitance inside the chip, since there is a limit to the chip size.
Further, when the MMIC is mounted in a six-pin package, it is necessary that the RF terminal 201 be opposed to the other RF terminals 202 and 203, for example, as shown in FIG. 1D. Further, it is preferable that the wire connected to the RF terminal 201 be prevented from crossing over the wire connected to the DC terminal of the switch section or any wires of the inverter circuit. In the conventional circuit configuration, the wiring must be detoured around in order to prevent crossing of the wires. Consequently, the problem of an increase in chip size arises.